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A 23.5 GHz Double Stage Low Noise Amplifier Using .13μm CMOS Process with an Innovative Inter-Stage Matching Technique

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4 Author(s)
Rashid, S.M.S. ; Dept. of Electr. & Electron. Eng., Bangladesh Univ. of Eng. & Technol., Dhaka, Bangladesh ; Roy, A. ; Ali, S.N. ; Rashid, A.B.M.H.

This paper demonstrates a 23.5 GHz double stage low noise amplifier using an innovative inter-stage matching technique. The same matching technique is also used at the output of the amplifier for the purpose of output matching. The circuit is designed in IBM .13 mum CMOS process and is simulated using cadence spectre. The simulated responses exhibit a forward gain of 20 dB at 23.5 GHz with a bandwidth of 2.5 GHz. Reverse isolation is less than -47.1 dB. Input and output matching parameters are -23 dB and -28.34 dB respectively. The amplifier achieves a NF of only 4.945 dB at the center frequency and consumes 21.7 mW of power when driven from a 1.2 V power supply. To the best of the authors' knowledge, double stage low noise amplifier of such high gain and low noise is rarely reported.

Published in:

Wireless Communications, Networking and Mobile Computing, 2009. WiCom '09. 5th International Conference on

Date of Conference:

24-26 Sept. 2009