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An accurate scalable small-signal RF CMOS model applicable to high frequencies is developed using 3-D electromagnetic (EM)-based extraction of parasitic elements. Due to multimetal layers, vertical interconnects, substrate loss and substrate-contact rings, the extrinsic parasitic network of CMOS field-effect transistor (FET) is more complicated than GaAs FETs and does not follow simple scaling rules. In this work, we have employed 3-D EM simulation to derive the scaling rules of the CMOS FETs. After de-embedding the effects of the pads and the interconnect lines using a pair of dummy patterns with different reference planes, the layout-dependent extrinsic network parameters are extracted using 3-D full-wave EM simulations. Based on the extracted parameters, new scaling rules are proposed for the extrinsic networks for 0.13 and 0.18 ??m CMOS processes. A complete scalable RF CMOS model is constructed by combining the scalable extrinsic network with the intrinsic CMOS network, and has been validated by comparing the predicted and measured S-parameters of the scaled devices from a family of 0.18 and 0.13 ??m CMOS FETs up to 50 and 75 GHz, respectively. In order to validate the scalable models for circuit applications, 30 and 60 GHz small-signal amplifiers have been designed using optimum size devices predicted from the scalable models. The measured results of the circuits are in good agreement with the simulation, validating the proposed modeling methods.