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An On-Chip NBTI Sensor for Measuring pMOS Threshold Voltage Degradation

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3 Author(s)
John Keane ; Dept. of Electr. & Comput. Eng., Univ. of Minnesota, Minneapolis, MN, USA ; Tae-Hyoung Kim ; Chris H. Kim

Negative bias temperature instability (NBTI) is one of the most critical device reliability issues in sub-130 nm CMOS processes. In order to better understand the characteristics of this mechanism, accurate and efficient means of measuring its effects must be explored. In this work, we describe an on-chip NBTI degradation sensor using a delay-locked loop (DLL), in which the increase in pMOS threshold voltage due to NBTI stress is translated into a control voltage shift in the DLL for high sensing gain. The proposed sensor is capable of supporting both DC and AC stress modes. Measurements from a test chip fabricated in a 130 nm bulk CMOS process show an average gain of 10 in the operating range of interest, with measurement times in tens of microseconds possible for minimal unwanted threshold voltage recovery. NBTI degradation readings across a range of operating conditions are presented to demonstrate the flexibility of this system.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:18 ,  Issue: 6 )