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An experimental chip to evaluate test techniques experiment results

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3 Author(s)
S. C. Ma ; Center for Reliable Comput., Stanford Univ., CA, USA ; P. Franco ; E. J. McCluskey

This paper describes the testing of a chip especially designed to facilitate the evaluation of various test techniques for combinational circuitry. The different test sets and test conditions are described. Several tables show the results of voltage tests applied, either at rated speed or 2/3 speed, to each defective CUT. Data for CrossCheck, Very-Low-Voltage, IDDQ and delay tests are also given

Published in:

Test Conference, 1995. Proceedings., International

Date of Conference:

21-25 Oct 1995