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Generic Self-Adaptation to Reduce Design Effort for System-on-Chip

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3 Author(s)
Bernauer, A. ; Dept. of Comput. Eng., Univ. of Tubingen, Tubingen, Germany ; Bringmann, O. ; Rosenstiel, W.

We investigate a generic self-adaptation method to reduce the design effort for system-on-chip (SoC). Previous self-adaptation solutions at chip-level use circuitries which have been specially designed for the current problem by hand, leading to an elaborate and inflexible design process, requiring specially trained engineers, and making design reuse difficult. On the other hand, a generic self-adaptation method that can be used for various self-adaptation problems promises to reduce the necessary design effort, but may come with reduced performance and other costs. In this paper, we analyze the performance, self-adaptation capabilities and costs of a generic self-adaptation method. The proposed method allows chip-level self-adaptation of a SoC, can tolerate unforeseen events, and can generalize from previous self-adaptation tasks. Furthermore, the method helps to improve the design process by allowing design reuse, providing generic applicability, and offering a uniform design process for various self-adaptation tasks. Simulation results show that the performance of our method lies only 10% below the performance of a perfect, non-adaptive system in the average case, and only 32% in the worst case. In case of unforeseen events, where the performance of a non-adaptive system decreases significantly, the method can keep its performance level by self-adaptation. We also compare other costs involved.

Published in:

Self-Adaptive and Self-Organizing Systems, 2009. SASO '09. Third IEEE International Conference on

Date of Conference:

14-18 Sept. 2009

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