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Design of a 60-GHz down-converting dual-gate mixer in 130-nm CMOS technology

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5 Author(s)
Hsin-Chih Kuo ; Dept. of Electr. Eng., Nat. Cheng Kung Univ., Tainan, Taiwan ; Chu-Yun Yang ; Jin-Fu Yeh ; Huey-Ru Chuang
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A 60-GHz down-converting dual-gate mixer, fabricated in the 0.13-μm CMOS process, for WPAN applications is presented. The mixer utilizes the dual-gate topology and adds a buffer to avoid loading effects. A good agreement between simulation and measurements is observed. The mixer exhibits a conversion loss of 2.7 dB, input 1-dB compression point of -8 dBm at RF of 60 GHz, IF of 5 GHz and LO power of 0 dBm. The total power consumption is 16.8 mW, 7.2 mW for the core mixer and 9.6 mW for the buffer.

Published in:
Microwave Conference, 2009. EuMC 2009. European

Date of Conference: Sept. 29 2009-Oct. 1 2009

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