By Topic

Microprocessor memory management units

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

1 Author(s)
Milenkovic, M. ; IBM Corp., Boca Raton, FL, USA

This tutorial describes the current crop of commercial memory management units (MMUs) for 32-bit microprocessors. The discussion includes both complex- and reduced-instruction-set computers (CISCs and RISCs). The rationale, principles, and issues related to hardware support for memory management and virtual memory are reviewed. The design and features of high-end microprocessor MMUs are reviewed and compared with respect to a common set of criteria. Special attention is paid to Unix requirements and multiprocessor, multiple MMU considerations. The MMUs covered are Intel 80386, i486, and i860; Motorola's 68851 (MMU for the 68020), 68030, 68040, and 88200 (MMU for the 88000 series); the Fujitsu MB86920 (Sparc MMU); and the MIPS R2000/R3000.<>

Published in:

Micro, IEEE  (Volume:10 ,  Issue: 2 )