Cart (Loading....) | Create Account
Close category search window
 

Optimization of the Thermomechanical Reliability of a 65 nm Cu/Low- k Large-Die Flip Chip Package

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

10 Author(s)
Ong, J.M.G. ; Chartered Semicond. Manuf., Ltd., Singapore, Singapore ; Tay, A.A.O. ; Zhang, X. ; Kripesh, V.
more authors

The trend toward finer pitch and higher performance integrated circuit devices has driven the semiconductor industry to incorporate copper and low-k dielectric materials. However, the low-k materials have lower modulus and poorer adhesion compared to the common dielectric materials. Thus, thermomechanical failure is one of the major bottlenecks in the development of Cu/low-k larger-die flip chip packages. This paper describes the optimization of the structural design of Chartered's C65 nm 21 mm times 21 mm die size flip-chip ball grid array package incorporated with fully active and functional ninemetal Cu/low-k layers and 150 mum interconnect pitch. The lowk material used in this paper is nonporous SiCOH with a k value of 2.9. A parametric study using 2-D plane strain finite element analysis was performed to study the effect of various parameters on the reliability of the large-die package in order to arrive at an optimized design. In order to have a simple criterion to predict the reliability of the yet-to-be-built largedie package, reliability tests were carried out on some existing 15 mm times 15 mm die CvJlow-k flip chip packages which were identical to the 21mm times 21mm die package except for the size. The packages were found to pass the reliability tests. 2-D plane strain finite element analyses were then performed on the 15 mm times 15 mm die. The computed delamination stresses at the low-k layer and the strain energy density dissipation per cycle in the critical solder (DeltaW) were then used as a benchmark for the design of a larger flip chip package. The efficacy of the polymer encapsulated dicing lane technology was established. In this paper, the effect of the number of fluorosilicate glass layers, die thickness, substrate thickness, Cu post height, and underfill type on the delamination stresses in the low-k layer and DeltaW were determined. Specimens of the optimized large-die package were then fabricated and subjected to reliability tests. They we- - re all found to pass the reliability tests. From these reliability tests, new benchmark values of the delamination stresses at the low-k layer and DeltaW are obtained, which can be used to aid in the design of large-die Cu/low-k flip chip packages.

Published in:

Components and Packaging Technologies, IEEE Transactions on  (Volume:32 ,  Issue: 4 )

Date of Publication:

Dec. 2009

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.