Skip to Main Content
This paper presents a novel approach to extending the life of current-based test techniques for the detection and diagnosis of bridging defects. Called CΔIDDQ (Complementary ΔIDDQ), this approach combines a modified test pattern generation with a simple post-processing of IDDQ measurements (namely additions and subtractions) such that the resulting measurement combination equals zero. Consequently, CΔIDDQ eliminates the main current variance sources: wafer-to-wafer, IC-to-IC and vector-to-vector variations; the only remaining source is the measurement variance. The modified test pattern generation is based on the innovative concept of transient-fault test pattern decomposition and the use of layout information to target realistic bridging defect sites. Verification based on logic simulation confirms that the combination of the resulting subset of fault-free IDDQ measurements is equal to 0. Using this promising new technique, bridging defect detection capability can be improved by orders of magnitude. Simulation results also show that this improved detection capability may be necessary even for low-power devices.