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A Scalable Circuit-Architecture Co-Design to Improve Memory Yield for High-Performance Processors

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3 Author(s)
Ndai, P. ; Sch. of Electr. & Comput. Eng., Purdue Univ., West Lafayette, IN, USA ; Goel, A. ; Roy, K.

Due to their small sizes, SRAMs are particularly vulnerable to parametric failures, resulting in significantly reduced yield. The underlying problem with SRAM is that there are conflicting requirements for read stability and writeability, such that optimizing the cell for read stability degrades its writeability. In this work, we present a circuit-architecture co-design technique that allows the decoupling of these conflicting requirements, resulting in significant yield enhancement at iso-area, while being scalable. Our technique is based on the observation that the write operation is not as performance critical as the read operation in high-performance microprocessors. Thus, the technique skews the cell design towards improving read stability at the circuit level at the expense of writeability. To handle the increased write failures in some dies, we apply simple architectural modifications that allow the write operation to take an additional cycle (stretched write cycle). By using our technique, we can improve yield from 37% to 69%, while having 3.4% performance impact on average, without increasing the size of the SRAM cell.

Published in:

Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:18 ,  Issue: 8 )