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Systolic array processors for 2D IIR spatio-temporal beamforming wave-digital filters (WDFs)

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2 Author(s)
Madanayake, H.L.P.A. ; ECE, Univ. of Calgary, Calgary, AB, Canada ; Bruton, L.T.

A systolic-array FPGA processor is proposed for implementing 2D IIR frequency-planar-beam wave digital filters (WDFs) to achieve directional enhancement of propagating broadband plane-waves based on their directions of arrival. The architecture is based on a passive LC ladder prototype network and has a high-throughput of one-frame-per-clock-cycle. The structural similarity between the 2D WDF, the 2D analog prototype and the proposed implementation leads to a massively-parallel realization. An example is provided of an implementation on a Xilinx Virtex-4 Sx35-10ff668 FPGA.

Published in:

Communications, Computers and Signal Processing, 2009. PacRim 2009. IEEE Pacific Rim Conference on

Date of Conference:

23-26 Aug. 2009