Systolic array processors for 2D IIR spatio-temporal beamforming wave-digital filters (WDFs)

A systolic-array FPGA processor is proposed for implementing 2D IIR frequency-planar-beam wave digital filters (WDFs) to achieve directional enhancement of propagating broadband plane-waves based on their directions of arrival. The architecture is based on a passive LC ladder prototype network and has a high-throughput of one-frame-per-clock-cycle. The structural similarity between the 2D WDF, the 2D analog prototype and the proposed implementation leads to a massively-parallel realization. An example is provided of an implementation on a Xilinx Virtex-4 Sx35-10ff668 FPGA.