By Topic

New processor array architecture for scalable radix 2 Montgomery modular multiplication algorithm

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Atef Ibrahim ; Electronics Research Institute, Cairo, Egypt ; Fayez Gebali ; Hamed Elsimary ; Amin Nassar

This paper presents a new processor array architecture for scalable radix2 Montgomery modular multiplication algorithm. In this architecture, the multiplicand and the modulus words are allocated to each processing element rather than pipelined between the processing elements as in the previous architecture extracted by C. Koc, and also the multiplier bits are fed serially to the first processing element of the processor array every odd clock cycle. By analyzing this architecture, we found that it has a better performance - in terms of area and speed - than the previous architecture extracted by C. Koc.

Published in:

2009 IEEE Pacific Rim Conference on Communications, Computers and Signal Processing

Date of Conference:

23-26 Aug. 2009