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Scalable High Throughput and Power Efficient IP-Lookup on FPGA

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2 Author(s)
Hoang Le ; Ming Hsieh Dept. of Electr. Eng., Univ. of Southern California, Los Angeles, CA, USA ; Viktor K. Prasanna

Most high-speed Internet Protocol (IP) lookup implementations use tree traversal and pipelining. Due to the available on-chip memory and the number of I/O pins of Field Programmable Gate Arrays (FPGAs), state-of-the-art designs cannot support the current largest routing table(consisting of 257 K prefixes in backbone routers). We propose a novel scalable high-throughput, low-power SRAM-based linear pipeline architecture for IP lookup. Using a single FPGA, the proposed architecture can support the current largest routing table, or even larger tables of up to 400 K prefixes. Our architecture can also be easily partitioned, so as to use external SRAM to handle even larger routing tables (up to 1.7 M prefixes). Our implementation shows a high throughput (340 mega lookups per second or 109 Gbps), even when external SRAM is used. The use of SRAM (instead of TCAM) leads to an order of magnitude reduction in power dissipation. Additionally, the architecture supports power saving by allowing only a portion of the memory to be active on each memory access. Our design also maintains packet input order and supports in-place non-blocking route updates.

Published in:

Field Programmable Custom Computing Machines, 2009. FCCM '09. 17th IEEE Symposium on

Date of Conference:

5-7 April 2009