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Exploiting Matrix Symmetry to Improve FPGA-Accelerated Conjugate Gradient

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2 Author(s)
Bakos, J.D. ; Dept. of Comput. Sci. & Eng., Univ. of South Carolina, Columbia, SC, USA ; Nagar, K.K.

In this paper we describe a new approach for accelerating the Conjugate Gradient (CG) method using an FPGA co-processor. As in previous approaches, our co-processor performs a double-precision sparse matrix-vector multiplication. However, our implementation doubles the amount of computation per unit of input data by exploiting the symmetry of the input matrix and computing the upper and lower triangle of the input matrix in parallel. Using a Virtex-2 Pro 100 FPGA, we have achieved an observed computational throughput of 1155 MFLOPS.

Published in:

Field Programmable Custom Computing Machines, 2009. FCCM '09. 17th IEEE Symposium on

Date of Conference:

5-7 April 2009