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Mapping applications that consist of a collection of cores to FPGA accelerators and optimizing their performance is a challenging task in high performance reconfigurable computing. We present IMORC, an architectural template and highly versatile on-chip interconnect. IMORC links provide asynchronous FIFOs and bitwidth conversion which allows for flexibly composing accelerators from cores running at full speed within their own clock domains, thus facilitating the re-use of cores and portability. Further, IMORC inserts performance counters for monitoring runtime data. In this paper, we introduce the IMORC architectural template and the on-chip interconnect and demonstrate IMORC on the example of accelerating the k-th nearest neighbor thinning problem on an XtremeData XD1000 reconfigurable computing system.