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Design Exploration for FPGA-Based Multiprocessor Architecture: JPEG Encoding Case Study

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4 Author(s)
Wu, J. ; Sch. of Inf. Technol. & Electr. Eng., Univ. of Queensland, Brisbane, QLD, Australia ; Williams, J. ; Bergmann, N. ; Sutton, P.

This paper presents a system level design flow which enables rapid design space exploration and a verification tool to assist a designer to identify an FPGA-based MPSoC for stream-oriented application. The case study, JPEG encoding, illustrates how the tool exploits the task-level parallelism and produces a suitable architectural design, binding and scheduling algorithm while satisfying physical constraints.

Published in:

Field Programmable Custom Computing Machines, 2009. FCCM '09. 17th IEEE Symposium on

Date of Conference:

5-7 April 2009