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A low power Class D audio amplifier with discrete time loop filter compensation

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2 Author(s)
Forzley, T. ; Dept. of Electron., Carleton Univ., Ottawa, ON, Canada ; Mason, R.

This brief describes a new Class D amplifier topology with digital input and a digital compensation loop filter to improve linearity. The core of the system is a high resolution hybrid multi-bit SigmaDelta-Pulse Width Modulation (PWM) modulator. The modulator does not require dynamic element matching nor signal processing to correct for distortion arising from the discrete PWM process. A system prototype based on a FPGA and commercial 16b analog to digital converter (ADC) validate the system design before implementation in 0.13 mum CMOS. Measurement results at 1 kHz yield a Total Harmonic Distortion (THD) better than 0.03% and greater than 30 dB of noise rejection and linearity enhancement. The system is inherently scalable to deep submicron processes due to its predominately digital architecture.

Published in:

Circuits and Systems and TAISA Conference, 2009. NEWCAS-TAISA '09. Joint IEEE North-East Workshop on

Date of Conference:

June 28 2009-July 1 2009

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