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To realize the on-chip temperature monitoring of VLSI circuits, an accurate time-domain low-power CMOS thermostat based on delay lines is proposed. Contrary to the voltage-domain predecessors, the proposed circuit can benefit from the performance enhancement due to the scaling down of fabrication processes. By replacing R-string voltage division and voltage comparator with delay line time division and time comparator, only little static power is consumed. The power consumption and chip size can be reduced substantially. Without any bipolar transistor, the temperature sensor composed of a delay line is utilized to generate the delay time proportional to the measured temperature. Instead of a conventional voltage/current DAC or an external resistor, a succeeding multiplexer (MUX) along with a reference delay line is used to program the set-point. The test chips with mixed-mode design were fabricated in a TSMC CMOS 0.35-mum 2P4M digital process. The chip area is merely 0.4 mm2. The effective resolution is around 0.5degC with a 256-to-1 multiplexer and -40degC ~ 80degC nominal temperature range. The achieved measurement error is within plusmn0.8degC for a total of 20 packaged chips over the temperature operation range of commercial ICs. The power consumption is 0.45 muW per conversion and a measurement rate as high as 1 MHz is feasible when necessary.