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This paper presents a new and comprehensive low-power test scheme compatible with a test compression environment. The key contribution of this paper is a flexible test-application framework that achieves significant reductions in switching activity during all phases of scan test: loading, capture, and unloading. In particular, we introduce a new on-chip continuous-flow decompressor. Its synergistic use with a power-aware scan controller allows a significant reduction of toggling rates when feeding scan chains with decompressed test patterns. While the proposed solution requires minimal modifications of the existing design for test logic, experiments indicate that its use results in a low switching activity which reduces power consumption to or below a level of a functional mode. It resolves problems related to power dissipation, voltage drop, and increased temperature. Our approach integrates seamlessly with test logic synthesis flow, and it does not compromise compression ratios. It fits well into various design paradigms, including modular design flow where blocks come with individual decompressors and compactors.
Computer-Aided Design of Integrated Circuits and Systems, IEEE Transactions on (Volume:28 , Issue: 11 )
Date of Publication: Nov. 2009