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Background: III-V semiconductors are one of the most promising device candidates for future high-speed, low-power logic applications due to their high electron mobility. Recently, high performance III-V n-FETs have been demonstrated. However, for CMOS logic, there is a significant challenge of identifying high mobility III-V p-FET candidates. Strain in silicon initially in Si layers on relaxed SiGe buffer layers, later from SiGe spacers / spacer caps has been successful in significantly enhancing the pMOS performance and is now employed ubiquitously in the industry. Use of strain to reduce hole effective masses by splitting the heavy-hole (hh) and light-hole (Ih) valence bands was first demonstrated in p-channel InGaAs/ (Al)GaAs. More recently, the technique has been applied to strained InSb, GaSb and InGaSb based channels for improving hole nobility (muh). Given the many choices available for materials, stoichiometry, strain, channel orientation, a modeling effort is necessary to evaluate different options and narrow down the choice for experimentation.