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Deembedding Accuracy for Device Scale and Interconnection Line Parasitics

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5 Author(s)
Jaeho Lee ; Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea ; Jaehong Lee ; Jongwook Jeon ; Hee Sauk Jhon
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In this letter, we investigate the deembedding accuracy of open-short (OS) and pad-open-short (POS) deembedding for transistor measurement and modeling. It is found that all of the transistor intrinsic element values except for the gate-resistance, Rg , are independent of the deembedding procedure. Furthermore, the difference in Rg is dependent on the device size. To analyze the origin of the deembedding difference, the equivalent circuits of the PADs and interconnection lines are constructed from the measured data by varying the values of parasitic parameters.

Published in:

Microwave and Wireless Components Letters, IEEE  (Volume:19 ,  Issue: 11 )