Cart (Loading....) | Create Account
Close category search window
 

Deembedding Accuracy for Device Scale and Interconnection Line Parasitics

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Jaeho Lee ; Dept. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ., Seoul, South Korea ; Jaehong Lee ; Jongwook Jeon ; Hee Sauk Jhon
more authors

In this letter, we investigate the deembedding accuracy of open-short (OS) and pad-open-short (POS) deembedding for transistor measurement and modeling. It is found that all of the transistor intrinsic element values except for the gate-resistance, Rg , are independent of the deembedding procedure. Furthermore, the difference in Rg is dependent on the device size. To analyze the origin of the deembedding difference, the equivalent circuits of the PADs and interconnection lines are constructed from the measured data by varying the values of parasitic parameters.

Published in:

Microwave and Wireless Components Letters, IEEE  (Volume:19 ,  Issue: 11 )

Date of Publication:

Nov. 2009

Need Help?


IEEE Advancing Technology for Humanity About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies

A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2014 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.