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A novel current-mode, binary-tree WTA / LTA circuit for application in analog Kohonen neural networks has been presented. In the proposed circuit input currents are first converted to step signals with equal amplitudes and different delays that are proportional to the values of these currents. In the second step these delays are compared using a set of time domain comparators in the binary tree structure that allows to determine either the Min or the Max signal, depending on the configuration. The circuit realized in the TSMC CMOS 0.18 mum process offers a precision of about 99% at the data rate of 3.5 MSps and energy consumption of about 0.7 pJ per one input signal per cycle.