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Scalable 128-bit AES-CM crypto-core reconfigurable implementation for secure communications

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5 Author(s)
Astarloa, A. ; Dept. of Electron. & Telecommun., Univ. of the Basque Country, Bilbao, Spain ; Zuloaga, A. ; Lazaro, J. ; Jimenez, J.
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A novel cryptographic core (cryptocore) approach for secure communications is presented in this work. It is an AES-Counter Mode core for System-on-Programmable-Devices that takes advantage from the flexibility of the reconfigurable devices. The proposed architecture is parameterizable, so it is easily scalable to fulfill different target area-speed trade-offs. This parametrization affects both the number of AES cipher block processors running in parallel and the implementation type. The crypto-core supports three AES cipher blocks implementations publicly available. The proposed architecture is analyzed with experimental results that show how the crypto-core eases and optimizes the secure communications implementation in different systems.

Published in:

Applied Electronics, 2009. AE 2009

Date of Conference:

9-10 Sept. 2009