A symbolic-simulation approach to the timing verification of interacting FSMs

A timing verifier that scales to verify complex sequential circuits, modeled in terms of interacting FSMs, while rejecting false sequential and combinational paths has, so far, not been developed. We present an algorithm for this purpose. The inherently modular nature of interactions among FSMs, allow a highly efficient symbolic simulation verification methodology. Experimental results illustrate this methodology's ability to scale, while providing accurate timing verification results.