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Instruction scheduling for VLIW processors under variation scenario

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1 Author(s)
Mujadiya, N.V. ; Center for VLSI & Embedded Syst. Technol., Int. Inst. of Inf. Technol. - Hyderabad, Hyderabad, India

Process variations in components like adders, multipliers, etc., of different integer functional units (IFUs) in VLIW (very long instruction word) processors may cause these units to operate at various speeds, resulting in non-uniform latency IFUs. Worst-case techniques to deal with the non-uniform latency IFUs may incur significant performance and/or leakage energy loss. In this work, we propose two process variation-aware compile time techniques to handle non-uniform latency IFUs. In the first technique, namely `turn-off', we turn off all the process variation affected high latency IFUs. In the second technique, namely `on-demand turn-on', we use some of the process variation affected high latency IFUs by turning them on whenever there is a requirement. Our experimental results show that with these techniques, the non-uniform latency IFU can be tackled without much performance penalty. The proposed techniques also achieve significant reduction in leakage energy consumption because of turning off of some of the IFUs.

Published in:

Systems, Architectures, Modeling, and Simulation, 2009. SAMOS '09. International Symposium on

Date of Conference:

20-23 July 2009

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