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FPGA implementation of high-speed parallel maximum a posteriori (MAP) decoders

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7 Author(s)
del Barco, M.I. ; Digital Commun. Res. Lab., Nat. Univ. of Cordoba, Cordoba, Argentina ; Maggio, G.N. ; Morero, D.A. ; Fernandez, J.
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This paper presents an efficient parallel architecture for high-speed maximum a posteriori (MAP) probability detectors. The parallel systolic scheme proposed here builds upon a sliding window approach, and is capable of providing very high throughput. The implementation of an 8-state MAP decoder on an off-the-shelf field programmable gate array (FPGA) achieves a throughput of 1.6 Gb/s. The MAP detector is well-known as the optimal solution to minimize the bit-error-rate (BER). Moreover, when used for equalization on iterative detectors (i.e., turbo equalizers), the MAP algorithm can achieve a performance near Shannon's channel capacity. Thus, the scheme described in this work results highly attractive to efficiently mitigate channel impairments found on high-speed optical fiber systems and other high speed communication applications.

Published in:

Micro-Nanoelectronics, Technology and Applications, 2009. EAMTA 2009. Argentine School of

Date of Conference:

1-2 Oct. 2009