Performance of a simple architecture of an analog CMOS detector for MB-UWB receiver

This paper presents an implementation study of an analog CMOS pulse detector. The detector includes four stages: squarer, current amplification, an integrator and a sample and hold. The main objective is to realize the pulse detection function with less complexity design, low power consumption and low mass fabrication cost. Also, it must operates in the 3.1–10.6 GHz UWB band for a multi-band impulse radio receiver. The noise performance of the detector is studied. Transistors mismatches and imperfection of the current amplifier are theoretically studied in order to evaluate their effects on the global circuit performances. CADENCE's spectre simulation results in 0.35 µm CMOS technology are presented to validate this approach. Monte-Carlo simulation results are equally given in order to enforce the analytical studies. The proposed detector consumes only 2 mW with a ±1.8 V supply.