By Topic

Performance of a simple architecture of an analog CMOS detector for MB-UWB receiver

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Mroué, M. ; SUPELEC-IETR, Cesson-Sevigne, France ; Haese, S. ; Mallegol, S. ; Paquelet, S.
more authors

This paper presents an implementation study of an analog CMOS pulse detector. The detector includes four stages: squarer, current amplification, an integrator and a sample and hold. The main objective is to realize the pulse detection function with less complexity design, low power consumption and low mass fabrication cost. Also, it must operates in the 3.1-10.6 GHz UWB band for a multi-band impulse radio receiver. The noise performance of the detector is studied. Transistors mismatches and imperfection of the current amplifier are theoretically studied in order to evaluate their effects on the global circuit performances. CADENCE's spectre simulation results in 0.35 mum CMOS technology are presented to validate this approach. Monte-Carlo simulation results are equally given in order to enforce the analytical studies. The proposed detector consumes only 2 mW with a plusmn1.8 V supply.

Published in:

Ultra-Wideband, 2009. ICUWB 2009. IEEE International Conference on

Date of Conference:

9-11 Sept. 2009