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A Layer-Multiplexed 3D On-Chip Network Architecture

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2 Author(s)
Ramanujam, R.S. ; Dept. of Electr. & Comput. Eng., Univ. of California, La Jolla, CA, USA ; Bill Lin

Programmable many-core processors are poised to become a major design option for many embedded applications. In the design of power-efficient embedded many-core processors, the architecture of the on-chip network plays a central role. Many designs have relied on a 2D mesh architecture as the underlying communication fabric. With the emergence of 3D technology, new on-chip network architectures are possible. In this paper, we propose a novel layer-multiplexed (LM) 3D network architecture that takes advantage of the short interlayer wiring delays enabled in 3D technology. In particular, the LM architecture replaces the one-layer-per-hop routing in a conventional 3D mesh with simpler vertical demultiplexing and multiplexing structures. When combined with a layer load-balanced oblivious routing algorithm, it can achieve the same worst-case throughput as the best known oblivious routing algorithm on a conventional 3D mesh. However, in comparison to a conventional 3D mesh, the LM architecture consumes 27% less power, attains 14.5% higher average throughput, and achieves 33% lower worst-case hop count on a 4 times 4 times 4 topology.

Published in:

Embedded Systems Letters, IEEE  (Volume:1 ,  Issue: 2 )

Date of Publication:

Aug. 2009

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