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Area-Efficient Scalable MAP Processor Design for High-Throughput Multistandard Convolutional Turbo Decoding

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3 Author(s)
Chen-Hung Lin ; Grad. Inst. of Electron. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Chun-Yu Chen ; An-Yeu Wu

Most of advanced wireless standards, such as WiMAX and LTE, have adopted different convolutional turbo code (CTC) schemes with various block sizes and throughput rates. Thus, a reconfigurable and scalable hardware accelerator for multistandard CTC decoding is necessary. In this paper, we propose scalable maximum a posteriori algorithm (MAP) processor designs which can support both single-binary (SB) and double-binary (DB) CTC decoding, and handle arbitrary block sizes for high throughput CTC decoding. We first propose three combinations of parallel-window (PW) and hybrid-window (HW) MAP decoding. Moreover, the computational modules and storages of the dual-mode (SB/DB) MAP decoding are designed to achieve a high area utilization. To verify the proposed approaches, a 1.28 mm 2 dual-mode 2PW-1HW MAP processor is implemented in 0.13 μ m CMOS process. The prototyping chip achieves a maximum throughput rate of 500 Mb/s at 125 MHz with an energy efficiency of 0.19 nJ/bit and an area efficiency of 3.13 bits/mm2 . For the multistandard systems, the expected throughput rates of the WiMAX and LTE CTC schemes is achieved by using five dual-mode 2PW-1HW MAP processors.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:19 ,  Issue: 2 )