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Asynchronous 2-D discrete cosine transform core processor

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3 Author(s)
B. Stott ; Dept. of Electr. & Comput. Eng., California Univ., Davis, CA, USA ; D. Johnson ; V. Akella

To lend additional insight into the reality of self-timed design, this paper proposes a large-scale, application specific, asynchronous design-a CCITT compatible asynchronous DCT/IDCT processor. The prototype DCT/IDCT processor uses two-phase transition signaling and a bounded delay approach to implement a modified version of Sutherland's micropipeline. The layout of the core processor was designed using standard cell and custom techniques to integrate 150,000 transistors in a 2 μ SCMOS technology. This investigation presents the prototype DCT/IDCT processor design and the resulting measures of speed, power, and area

Published in:

Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on

Date of Conference:

2-4 Oct 1995