By Topic

Formal Verification of SDG via Symbolic Model Checking

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Ning Ning ; Coll. of Autom., Northwestern Polytech. Univ., Xi''an, China ; Zhang Jun ; Xiang-Yang Gao ; Jing Xue

The computation temporal logic (CTL) is introduced to Signed Directed Graph (SDG) and a modeling and verifying method via Symbolic Model Checking is presented. The requirements and constrains of SDG are specified firstly, and the properties related to the fault propagation are extended, then the correctness properties of SDG are defined by CTL. Finally SDG is transferred into the SMV module through an algorithm SDG2SMV and verified automatically by using NuSMV. As a result of comparison, it is shown that the properties of SDG can be verified correctly and effectively.

Published in:

Intelligent Computation Technology and Automation, 2009. ICICTA '09. Second International Conference on  (Volume:4 )

Date of Conference:

10-11 Oct. 2009