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Rational clocking [digital systems design]

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3 Author(s)
L. F. G. Sarmenta ; Lab. for Comput. Sci., MIT, Cambridge, MA, USA ; G. A. Pratt ; S. A. Ward

Communication between independently-clocked digital subsystems typically involves a finite probability of synchronization failure whose minimization introduces delays and consequent performance costs. This paper explores a technique that eliminates both the inherent unreliability of such communication and the performance overhead it implies. Our approach maintains a known phase relationship, between clocks whose frequencies are related by a rational factor, and exploits the predictability of their relative phases to algorithmically time communications without run-time arbitration contests

Published in:

Computer Design: VLSI in Computers and Processors, 1995. ICCD '95. Proceedings., 1995 IEEE International Conference on

Date of Conference:

2-4 Oct 1995