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A Robust Edge Encoding Technique for Energy-Efficient Multi-Cycle Interconnect

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5 Author(s)
Jae-sun Seo ; Department of Electrical Engineering and Computer Science, University of Michigan, Ann Arbor, MI, USA ; Himanshu Kaul ; Ram Krishnamurthy ; Dennis Sylvester
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In this paper, we propose a new circuit technique for on-chip communication, the edge encoding technique, to reduce the energy consumption in multi-cycle interconnects. Both average and worst-case energy are reduced by desynchronizing the edges of rising and falling transitions. In a 1.2 V 65-nm CMOS technology, the proposed approach achieves up to 34% energy reduction with no latency overhead over optimally designed conventional busses due to coupling capacitance reductions. The technique further reduces energy consumption by 39% with iso-throughput at the expense of one-cycle latency. Energy savings are shown to be both larger and more robust to process, voltage, and temperature variations than previous techniques.

Published in:

IEEE Transactions on Very Large Scale Integration (VLSI) Systems  (Volume:19 ,  Issue: 2 )