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A Low-Jitter ADPLL via a Suppressive Digital Filter and an Interpolation-Based Locking Scheme

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2 Author(s)
Hsuan-Jung Hsu ; Dept. of Electr. Eng., Nat. Tsing-Hua Univ., Hsinchu, Taiwan ; Shi-Yu Huang

In this brief, we present a low-jitter and wide-range all-digital phase-locked loop (ADPLL). This ADPLL achieves low output clock jitter by a number of schemes. First, the phase is locked quickly through a predictive phase-locking scheme. Then, the jitter is further reduced by a suppressive digital loop filter. Finally, an interpolation-based locking scheme is utilized to enhance the resolution of the digitally controlled oscillator (DCO) so as to further reduce the phase error and jitter. Simulation results show that the jitter performance is very close to that of the free-running DCO. Measurement results show that the jitterPk-Pk and jitterRMS are 56 and 7.28 ps, respectively, when the output clock of the ADPLL is running at 600 MHz.

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Very Large Scale Integration (VLSI) Systems, IEEE Transactions on  (Volume:19 ,  Issue: 1 )