Referenced Items are not available for this document.
One of the challenges for 3D technology adoption is the insufficient understanding of 3D testing issues and the lack of DFT solutions. This article describes testing challenges for 3D ICs, including problems that are unique to 3D integration, and summarizes early research results in this area. Researchers are investigating various 3D IC manufacturing processes that are particularly relevant to testing and DFT. In terms of the process and the level of assembly that 3D ICs require, we can broadly classify the techniques as monolithic or as die stacking.
Published in:
Design & Test of Computers, IEEE
(Volume:26
,
Issue:
5
)
Date of Publication: Sept.-Oct. 2009
- Page(s):
- 26 - 35
- ISSN :
- 0740-7475
- INSPEC Accession Number:
- 10918032
- Digital Object Identifier :
- 10.1109/MDT.2009.125
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 13 October 2009
- Issue Date :
- Sept.-Oct. 2009
- Sponsored by :
- IEEE Council on Electronic Design and Automation
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