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This study proposes a new inter-signal timing skew compensation technique for parallel links with current-mode incremental signalling. The maximum deskew range is one bit time in both directions. Both the transmitters and receivers of the links are current-mode configured to take the advantages of current-mode signalling. Each receiver maps the direction of its channel current representing the logic state of the incoming data to two voltages of different values, enabling a convenient recovery of both the logic state and timing information of the received data. The feedback at the front-end of the receiver minimises the dependence of the input impedance of the receiver on the direction of the channel current so that data-dependent impedance mismatch is minimised. Inter-signal timing skews are compensated by inserting a delay line in each channel whose time delay is determined by the phase difference between the master sampling clock and data. A voltage replication circuit is proposed to copy the obtained optimal control voltage of the delay line of each channel so that the optimal deskew control voltage of the delay line is sustained. To assess the effectiveness of the proposed inter-signal timing skew compensation technique, a 2-bit 1 Gbytes/s parallel link has been implemented in UMC-0.13 mum 1.2 V CMOS technology and analysed using SpectreRF with BSIM3V3 device models. Simulation results demonstrate that the proposed inter-signal timing skew compensation method can compensate inter-signal timing skew up to one bit time in both directions.
Date of Publication: October 2009