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CMOS multiplier based on the relationship between drain current and inversion charge

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5 Author(s)
Machado, M.B. ; CEFET-RS/UNED Charqueadas, Charqueadas, Brazil ; Cunha, A.I.A. ; de Lacerda, L.A. ; Galup-Montoro, C.
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The authors propose a four-quadrant multiplier based on a core cell that exploits the general relationship between the saturation current of an MOS transistor and the source inversion charge density, valid from weak to strong inversion. The advantages of the proposed circuit are simplicity, low distortion and feasibility of low-voltage operation. Experimental results in a 0.35 mum CMOS prototype indicate 1 mA consumption for 1 MHz bandwidth, and distortion level below 1 for an input current of 80 of the full-scale range. The multiplier core area is around 10 000 m2.

Published in:

Circuits, Devices & Systems, IET  (Volume:3 ,  Issue: 5 )

Date of Publication:

October 2009

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