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Pricing the American Option Using Reconfigurable Hardware

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2 Author(s)
Wynnyk, C. ; Electr. Eng. Dept., RPI, Troy, NY, USA ; Magdon-Ismail, M.

We present a novel reconfigurable hardware architecture for accelerating American option pricing using the binomial lattice algorithm. The architecture provides double precision floating point pricing, evaluating up to N = 64,000 time steps in the binomial lattice. Advanced memory management techniques and optimized control logic allow for 4-way parallelism on a single-asset evaluation. These techniques achieve a 73-times speedup over an optimized CPU implementation, and a considerable improvement over the best previous reconfigurable hardware implementation. A significant advantage of our approach is that the speed up is on a per asset basis whereas all previous approaches on FPGA and GPU architectures achieve their speed up by evaluating many assets in parallel.

Published in:

Computational Science and Engineering, 2009. CSE '09. International Conference on  (Volume:2 )

Date of Conference:

29-31 Aug. 2009

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