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The increasing number of complex jobs scheduled to execute on embedded systems has increased the importance of fast response times in job scheduling and task switching on embedded processors. This paper addresses the issue of reducing context-switching overhead. We present a novel register file architecture, the paged register file (pRF), that comprises two novel mechanisms for reducing context-switching latency related to the hardware context: the valid-annotated register file and semishadowing. The valid-annotated register file contains valid bits to annotate the used registers, which can be used to reduce register accesses in context switching. Moreover, the utilization of the register file is increased by semishadowing, which allows two threads to share the same register file. Experimental results obtained on the XEEMU platform with the benchmarks, DSPstone, show that support for our proposed pRF design reduces the frequency of context-switching by around 24% and reduces the amount of register movements by 46.9%.