To minimize leakage currents resulting from the thinning of the insulator in the gate stack of field effect transistors, high-dielectric constant (high-k) metal oxides, and HfO2 in particular, are being implemented as a replacement for SiO2. To speed the rate of processing, it is desirable to etch the gate stack (e.g., metal gate, antireflection layers, and dielectric) in a single process while having selectivity to the underlying Si. Plasma etching using Ar/BCl3/Cl2 mixtures effectively etches HfO2 while having good selectivity to Si. In this article, results from integrated reactor and feature scale modeling of gate-stack etching in Ar/BCl3/Cl2 plasmas, preceded by photoresist trimming in Ar/O2 plasmas, are discussed. It was found that BCln species react with HfO2, which under ion impact, form volatile etch products such as BmOCln and HfCln. Selectivity to Si is achieved by creating Si–B bonding as a precursor to the deposition of a BCln polymer which slows the etch rate relative to HfO2. The low ion energies required to achieve this selectivity then challenge one to obtain highly anisotropic profiles in the metal gate portion of the stack. Validation was performed with data from literature. The effect of bias voltage and key reactant probabilities on etch rate, selectivity, and profile - are discussed.