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A design for-testability technique for shorts and bridging faults in BiCMOS logic families

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3 Author(s)
Raahemifar, K. ; Dept. of Electr. & Comput. Eng., Waterloo Univ., Ont., Canada ; Hessabi, S. ; Elmasry, M.I.

The paper provides the results of a simulation-based fault characterization study of BiCMOS logic families. The author shows that most of the shorts cause IDDQ faults, while open defects result in delay or stuck-open faults. The author proposes a design-for-testability technique for detecting short and bridging faults in CMOS/BiCMOS logic circuits. The impact of this circuit modification on the behavior of the circuit in normal mode is investigated

Published in:

Electrical and Computer Engineering, 1995. Canadian Conference on  (Volume:1 )

Date of Conference:

5-8 Sep 1995

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