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Frequency multipliers in CMOS are key blocks in new emerging applications at mu-waves and mm-waves. Classical solutions, in bipolar technology, exploit the steep non-linear I-V characteristic in order to generate output harmonics at multiples of the input signal frequency. This solution would lead to a very limited gain (or even loss) in CMOS. In this paper we propose a novel circuit topology where a differential pair, in push-push configuration, locks an LC oscillator over a wide frequency range. A behavioral model of the circuit is presented and simple design equations for locking range and output swing are derived. Prototypes, realized in a standard 0.13 mum CMOS technology, show 30% locking range around 13 GHz with 3 dBm input power. Suppression of the unwanted input signal and its 3rd harmonic is better than 45 dBc. Core power dissipation is 5.2 mW only, less than half compared with state of the art.