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A 6b 3GS/s flash ADC with background calibration

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4 Author(s)
Kijima, M. ; Fujitsu VLSI Ltd., Kasugai, Japan ; Ito, K. ; Kamei, K. ; Tsukamoto, S.

A 6b 3GS/s flash ADC is implemented in a 90 nm CMOS process. The proposed ADC is based on an interpolating flash architecture without a T/H. To overcome the offset mismatch among comparators, an interleaved offset-calibration system is applied. Each 1-bit interpolating unit consisting of two preamplifiers and three comparators takes turns at offset calibration in the background. The ADC achieves the ENOB of 5.8 bit at 3GS/s and the ERBW of 500 MHz while consuming 90 mW from a 1.2 V supply. The ADC occupies a 0.28 mm2 area.

Published in:

Custom Integrated Circuits Conference, 2009. CICC '09. IEEE

Date of Conference:

13-16 Sept. 2009

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