CMOS RF transmitter with integrated power amplifier utilizing digital equalization

A digitally equalized 3.5-GHz CMOS RF transmitter (TX) with integrated 23-dBm power amplifier (PA) in 0.13-µm CMOS is presented. I/Q mismatch and memoryless nonlinearities of the whole transmit path, including the severe amplitude and phase distortions of the on-chip Class-B PA, are compensated by a digital, two-dimensional look-up table (2-D LUT) adapted by an LMS algorithm. The equalization results in an efficient TX with minimum analog and RF complexity. When a 20-MHz, 64-QAM OFDM signal with 9.6-dB peak-to-average power ratio (PAPR) was transmitted, the measured average drain efficiency of the PA was 12.5% with a −29.6-dB EVM after equalization. An 8.7-dB EVM improvement was achieved with a regular baseband sample rate of 80 MS/s in a typical 802.11a transmitter. A peak drain efficiency of 55% and a 25-dBm saturated output power were also measured for the same PA in a stand-alone package.