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Tera-scale performance machine learning SoC with dual stream processor architecture for multimedia content analysis

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6 Author(s)
Tse-Wei Chen ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Chi-Sun Tang ; Sung-Fang Tsai ; Chen-Han Tsai
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A new SoC architecture for multimedia content analysis is implemented with 16 mm2 area in 90 nm CMOS technology. It focuses on the co-acceleration of computer vision and machine learning algorithms, and two stream processors with massively parallel processing elements are integrated to achieve tera-scale performance. In the dual processor architecture, the data are transferred between processors and the high bandwidth dual memory through the local media bus, which reduces the power consumption in the AHB data access. The power efficiency of the proposed machine learning SoC is 1.7 TOPS/W, and the area efficiency is 81.3 GOPS/mm2.

Published in:

Custom Integrated Circuits Conference, 2009. CICC '09. IEEE

Date of Conference:

13-16 Sept. 2009