By Topic

An ultra low power non-volatile memory in standard CMOS process for passive RFID tags

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Peng Feng ; Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China ; Yunlong Li ; Nanjian Wu

An ultra low power non-volatile memory is designed in a standard CMOS process for passive RFID tags. The memory can operate in a new low power operating scheme under a wide supply voltage and clock frequency range. In the charge pump circuit the threshold voltage effect of the switch transistor is almost eliminated and the pumping efficiency of the circuit is improved. An ultra low power 192-bit memory with a register array is implemented in a 0.18 muM standard CMOS process. The measured results indicate that, for the supply voltage of 1.2 volts and the clock frequency of 780 KHz, the current consumption of the memory is 1.8 muA (3.6muA) at the read (write) rate of 1.3 Mb/s (0.8 Kb/s).

Published in:

2009 IEEE Custom Integrated Circuits Conference

Date of Conference:

13-16 Sept. 2009