Referenced Items are not available for this document.
A multi-stage replica bitline technique for reducing access time by suppressing enable timing variation of a sense amplifier was developed. Applied to a 288-kbit SRAM of the 40-nm process node, this technique achieves 6.1% access time reduction by reducing the sense-amplifier timing variation by 43%.
Published in:
Custom Integrated Circuits Conference, 2009. CICC '09. IEEE
Date of Conference: 13-16 Sept. 2009
- Page(s):
- 701 - 704
- E-ISBN :
- 978-1-4244-4073-3
- Print ISBN:
- 978-1-4244-4071-9
- INSPEC Accession Number:
- 10908866
- Conference Location :
- San Jose, CA
- Digital Object Identifier :
- 10.1109/CICC.2009.5280731
- Product Type:
- Conference Publications
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