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The SDR0 (Sparsified Digital Readout) prototype is a proof-of-principle design which is aimed at studying the feasibility of pixel level sparsified digital readout in CMOS MAPS matching the requirements for the Vertex Detector at the International Linear Collider. The deep n-well (DNW) available in deep sub-micron CMOS processes is used to collect the charge released in the substrate, and signal processing is performed by a classical optimum amplifying stage for capacitive detectors. The chip has been designed in a 130 nm triple-well CMOS process and fabricated by STMicroelectronics. This first prototype includes a 16 times 16 DNW-MAPS matrix with sparsified readout architecture, an 8 times 8 matrix with digital output and selectable access to the analog output in each cell, and a 3 × 3 matrix with all the analog outputs available at the same time. The analog front-end has been characterized and the digital readout circuits have been successfully tested at frequencies up to 50 MHz. The circuit design and the performance of SDR0 are discussed in this paper.