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An 8.9-megapixel 60-frames/s video image sensor with a 14-b column-parallel analog-to-digital converter (ADC) has been developed. A gain amplifier, a 14-b successive approximation ADC (SA-ADC), and a new column digital processor are employed in each column. The SA-ADC has sufficient operation speed to convert the pixel reset and the pixel signal into digital data in a row operation cycle. The column digital processor receives bit serial data from the SA-ADC output and performs subtraction of the reset data from the signal data in order to reduce column fixed pattern noise (FPN). Column FPN is successfully reduced to 0.36 erms - by this digital-domain column FPN correction. Low-voltage low-power serial video interface and noise decoupling on pixel drive voltages contribute to row-temporal-noise reduction to 0.31 erms -. Both column FPN and row temporal noise are not visible in spite of a low readout noise floor of 2.8 erms -.