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A 1.8-GHz CMOS Power Amplifier Using Stacked nMOS and pMOS Structures for High-Voltage Operation

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3 Author(s)
Ki Yong Son ; Sch. of Electr. Eng. & Comput. Sci., Korea Adv. Inst. of Sci. & Technol. (KAIST), Daejeon, South Korea ; Changkun Park ; Songcheol Hong

A class-E power amplifier is proposed in this study. It uses both nMOS and pMOS as switching devices to reduce the voltage stress of each transistor. A voltage-combining scheme with nMOS and pMOS is proposed, and a transformer is designed using this scheme. The power amplifier is implemented in a 0.18-mum RF CMOS process. Measurements show a maximum output power of 30.2 dBm with 36.8% power-added efficiency at a 3.3-V supply voltage. The power amplifier sustains a supply voltage of up to 3.9 V.

Published in:

Microwave Theory and Techniques, IEEE Transactions on  (Volume:57 ,  Issue: 11 )